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In computing, bus mastering is a feature supported by many bus architectures that enables a device connected to the bus to initiate transactions. It is also referred to as "first-party DMA", in contrast with "third-party DMA" where a system DMA controller (also known as peripheral processor, I/O processor, or channel) actually does the transfer. Some types of buses allow only one device (typically the CPU, or its proxy) to initiate transactions. Most modern bus architectures, such as PCI, allow multiple devices to ''bus master'' because it significantly improves performance for general purpose operating systems. Some real-time operating systems prohibit peripherals from becoming bus masters, because the scheduler can no longer arbitrate for the bus and hence cannot provide deterministic latency. While bus mastering theoretically allows one peripheral device to directly communicate with another, in practice almost all peripherals master the bus exclusively to perform DMA to main memory. If multiple devices are able to master the bus, there needs to be a bus arbitration scheme to prevent multiple devices attempting to drive the bus simultaneously. A number of different schemes are used for this; for example SCSI has a fixed priority for each SCSI ID. PCI does not specify the algorithm to use, leaving it up to the implementation to set priorities. ==References== * (How Bus Mastering Works ) - Tweak3D * (What is bus mastering? )- Brevard User's Group 抄文引用元・出典: フリー百科事典『 ウィキペディア（Wikipedia）』 ■ウィキペディアで「bus mastering」の詳細全文を読む スポンサード リンク
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